The invention relates to a ferroelectric transistor that has two source/drain regions, a channel region, a gate electrode, and a layer of ferroelectric material provided between the gate electrode and the channel region. The conductivity of this transistor is dependent on the state of polarization of the layer of ferroelectric material. Ferroelectric transistors of this type are being investigated with regard to non-volatile memories. This involves assigning two different states of polarization of the layer of ferroelectric material to two different logical values of a digital item of information. Other possible applications for ferroelectric transistors of this type are, for example, in neural networks.
It is known (see for example T. Nakamura, Y. Nakao, A. Kamisawa, H. Takasu: A Single Transistor Ferroelectric Memory Cell, IEEE, ISSCC, 1995, pages 68 to 69), to use ferroelectric transistors as memory cells of a memory cell configuration. In this case, each of the ferroelectric transistors is connected between a supply voltage line and a bit line. The selection takes place via a back gate. The ferroelectric transistors used have a floating gate electrode between the ferroelectric layer and the gate oxide. The charge of the floating gate electrode is controlled via the state of polarization of the ferroelectric layer.
It has been found that, when reading the information, voltage drops occur even at non-selected memory cells and this may lead to a falsification of the information stored in the individual memory cells. This falsification is attributed to the fact that flipping processes of the domains in ferroelectric materials are of a random nature and can be induced even at low voltages.
It is accordingly an object of the invention to provide a ferroelectric transistor and a method of producing the transistor which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide a ferroelectric transistor which is suitable as a memory cell of a memory cell configuration and in which changing of the written information during the reading operation is avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention a ferroelectric transistor that has two source/drain regions, which are configured in a semiconductor substrate. All semiconductor materials, in particular monocrystalline silicon, are suitable as the semiconductor substrate. The semiconductor substrate may in this case be both a monocrystalline silicon wafer and a SOI substrate. Configured on the surface of the semiconductor substrate between the two source/drain regions is a first gate intermediate layer and a first gate electrode. The first gate intermediate layer contains at least one ferroelectric layer. Configured between the source/drain regions, in the direction of a joining line between the source/drain regions, there is in addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.
In this ferroelectric transistor, the first gate electrode and the second gate electrode are configured next to each other along the joining line between the source/drain regions. The channel region of the ferroelectric transistor is consequently subdivided. One part of the channel region, which is configured under the first gate electrode, is capable of being activated by the charge effective at the first gate electrode. Another part of the channel region, which is configured under the second gate electrode, is capable of being activated by the charge effective at the second gate electrode. Current can flow between the source/drain regions only when both the part of the channel region below the first gate electrode and the part of the channel region below the second gate electrode are conducting.
The diode structure is polarized in such a way that, when a voltage is present at the second gate electrode, the conductivity of the channel region under the second gate electrode is controlled, the diode structure blocks, and as a result, the first gate electrode is isolated from this voltage.
When the ferroelectric transistor is being used as a memory for digital information, two states of polarization are assigned to the logical values in the ferroelectric layer. In the case of one state of polarization, the channel region below the first gate electrode and the ferroelectric layer is conducting, in the case of the other state it is not.
Since the first gate electrode and the second gate electrode are configured next to each other in the direction of the joining line between the source/drain regions, the activation by the second gate electrode is adequate for performing the reading operation. Dependent on the state of polarization of the ferroelectric layer, the channel region below the first gate electrode is or is not conducting. By activating the second gate electrode in such a way that the transistor in the region of the second gate electrode is turned on, the information is read out, and it is assessed whether a current is or is not flowing via the transistor.
The diode structure which is configured between the first gate electrode and the second gate electrode ensures that the voltage for activating the second gate electrode drops only over the second gate electrode. The first gate electrode is isolated from this voltage via the diode structure, so that no voltage drops over the ferroelectric layer. As a result, changing of the polarization of the ferroelectric layer, and consequently of the stored information, is avoided.
Alternatively, a voltage may be applied to the second gate electrode in order to polarize the ferroelectric layer. This is used for writing and erasing information.
Writing of information takes place in this case by a voltage which is greater than the reverse voltage of the diode structure and which polarizes the ferroelectric layer in one direction.
Erasing of the information takes place by a voltage with a different algebraic sign, so that the diode structure is polarized in the conducting direction and the voltage dropping across the ferroelectric layer polarizes the latter in the other direction.
The terms writing and erasing of information can also be used vice versa in this connection.
In accordance with an added feature of the invention, the second gate intermediate layer and the second gate electrode are respectively made up of two substructures which are configured mirror-symmetrically in relation to the first gate intermediate layer. The two substructures of the second gate electrode are electrically connected to each other. This configuration has the advantage that the voltage present across the second gate electrode induces, during the reading operation, an electric field of such a kind that the ferroelectric layer lies on an equipotential line and consequently no change in the polarization of the ferroelectric layer occurs. This configuration of the invention is particularly insensitive to disturbances.
In accordance with an additional feature of the invention, a dielectric layer is provided between the surface of the semiconductor substrate and the ferroelectric layer. This facilitates the application of the ferroelectric layer.
In accordance with another feature of the invention, the dielectric layer which is configured in the first gate intermediate layer between the semiconductor surface and the ferroelectric layer, and the dielectric layer which is a component part of the second gate intermediate layer are formed as a continuous electrical layer. The stack including the ferroelectric layer and the first gate electrode is produced on the surface of the continuous electrical layer.
In accordance with a further feature of the invention, the first gate electrode and/or the second gate electrode are part of the diode structure. In this way, the space requirement of the diode structure is reduced.
In accordance with a further added feature of the invention, the first gate electrode has polycrystalline silicon which is doped of a first conductivity type. The second gate electrode likewise has polycrystalline silicon which is doped of a second conductivity type, opposite that of the first type. The first gate electrode is in this case adjacent to the second gate electrode, so that the diode structure is formed by the first gate electrode and the second gate electrode. In this configuration, only three terminals are required for the operation of the ferroelectric transistor, two at the source/drain regions and one at the second gate electrode. Alternatively, in this configuration the first gate electrode and the second gate electrode can be respectively formed by correspondingly doped epitaxially grown silicon.
In accordance with a further additional feature of the invention, an auxiliary layer, for example of platinum, is provided between the ferroelectric layer and the first gate electrode. The auxiliary layer avoids undesired properties of the ferroelectric layer, such as for example, fatigue or imprint resistance.
In accordance with yet another feature of the invention, the first gate intermediate layer contains a dielectric layer of CeO2, ZrO2, Y2O3, or another oxide with the greatest possible dielectric susceptibility, for example SrTiO3. For the dielectric layer in the second gate intermediate layer, SiO2, CeO2, ZrO2, Y2O3, or another oxide with the greatest possible dielectric susceptibility, for example SrTiO3, is suitable. The ferroelectric layer may be composed of, inter alia, strontium-bismuth-tantalum (SBT), lead-zirconium-titanate (PZT), lithium niobate (LiNbO3) or barium-strontium-titanate (BST).
With the foregoing and other objects in view there is also provided, in accordance with the invention, a memory cell configuration including a plurality of memory cells that include the above described ferroelectric transistor.
With regard to the interference immunity of the memory cell configuration during the reading, writing and erasing of information, it is advantageous, in this case, to provide each memory cell with, in addition to the ferroelectric transistor, a selection transistor having a control electrode. In addition, the memory cell configuration has word lines, bit lines and supply lines, the word lines cross the supply lines and the bit lines. The ferroelectric transistor of one of the memory cells is, in each case, connected between two neighboring bit lines. The selection transistor is connected between the second gate electrode and one of the supply voltage lines. The control electrode of the selection transistor is respectively connected to one of the word lines.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method of producing a ferroelectric transistor, which includes: providing a semiconductor substrate with a surface; applying, to the surface of the semiconductor substrate, a dielectric layer, a ferroelectric layer, and a first electrode layer; structuring the first electrode layer and the ferroelectric layer together to produce a first gate electrod; applying and structuring a second electrode layer to produce a second gate electrode adjacent and laterally overlapping the first gate electrode; and providing the first gate electrode and the second gate electrode from materials that are matched to each other in such a way that the first gate electrode and the second gate electrode form a diode structure.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method of producing a ferroelectric transistor, which includes: providing a semiconductor substrate with a surface; applying, to the surface of the semiconductor substrate, a first gate intermediate layer, a ferroelectric layer, and a first electrode layer; structuring the first electrode layer the ferroelectric layer, and the first electrode layer together to produce a first gate electrode; producing a second gate intermediate layer disposed laterally relative to the first gate intermediate layer; providing the second gate intermediate layer with a dielectric layer; applying and structuring a second electrode layer to produce a second gate electrode adjacent and laterally overlapping the first gate electrode; and providing the first gate electrode and the second gate electrode from materials that are matched to each other in such a way that the first gate electrode and the second gate electrode form a diode structure.
In accordance with a concomitant feature of the invention, the method includes steps of, applying an auxiliary layer between the ferroelectric layer and the first electrode layer; and structuring the auxiliary layer when performing the step of structuring the ferroelectric layer and the first electrode layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a ferroelectric transistor, use thereof in a memory cell configuration and method of producing it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.